1. Field of the Invention
The present invention relates to a digital phase locked loop (PLL) circuit.
2. Description of the Related Art
A usual digital PLL circuit is for example comprised of a phase comparator, a digital counter, a frequency multiplier, and a frequency divider. It compares the phase of a reference clock and a return loop by the phase comparator, sets the data of the digital counter so as to minimize the phase error, and decides on the multiplying factor of the frequency multiplier or the dividing factor of the frequency divider based on that set data. To reduce the jitter, however, the number of bits of the digital counter must be increased. If the number of bits is increased, however, it takes time to minimize the phase error. That is, there is an inverse relationship between the reduction of the jitter and the reduction of the time taken for phase locking.